1. Field of the Invention
The present invention relates to a circuit which generates and distributes high-speed and high-accuracy clock signals for analog circuits and digital circuits. In particular, the present invention relates to a technology for a high-speed interface circuit, a processor, and a clock distribution circuit that requires high-frequency clock signals.
2. Description of the Related Art
Conventionally, multiple-stage buffer transmission is the most commonly employed clock signal distribution method wherein transmission is performed by connecting buffers in multiple stages. The multiple-stage buffer transmission method is widely used to provide clock signals with the desired amplitude and common-mode voltage to a circuit requiring clock signals under various process conditions.
FIG. 1 shows an example of a conventional clock signal distribution configuration. In the example configuration, a clock signal with relatively large amplitude, generated in a VCO (voltage-controlled oscillator) 72 within a PLL (phase-locked loop) 71 is transmitted to a circuit 76 through inverters 75 in a clock tree. The PLL 71 comprises a block to which a reference clock signal and a reproduction clock signal are input and the corresponding phase and frequency are detected., a block for comparing the results thereof, and a PFD/CP/LP circuit 74 having a loop filter for generating VCO control voltage and the like. The PLL 71 further comprises an N divider 73. The clock signal generated in the PLL 71 is provided to a plurality of inverters 75 in the next stage (B-stage) via a CMOS (complementary metal-oxide semiconductor) inverter 75 (A-stage). The attributes of each inverter 75 in the B-stage are mutually equal and the lengths of wiring to each inverter 75 are also mutually equal. The output clock signal output, wherein the signal is converted to normal rotation by the inverters 75 in B-stage and outputted, is configured to be mutually equal to the gate delay time. In addition, the output clock signal output is also configured to be mutually equal to the gate delay time in the path of the output clock signal in the C-stage and D-stage.
Therefore, the output clock signals are outputted respectively from each inverter 75 to the corresponding output terminal. The differences in the timing of clock skew of the output clock signals are suppressed and the phases of the output clock signals match each other. Subsequently, the signals are provided to each output clock signal load circuit 76.
However, the load capacity which can be driven by a single inverter 75 is limited, and therefore clock signals are handled by the clock distribution circuit and the like according to the load capacity to provide with clock signals in integrated circuits which perform digital signal processing by clock synchronization and the like. Although not shown, in order to increase the number of outputs in clock distribution circuits such as this, three inverters are further provided respectively in the latter stage of the inverter, and in addition, corresponding inverters for phase adjustment are provided in the earlier stage or the latter stage. In this way, a method for outputting a lot of clock signals with reduced clock skew to the load circuit 76 respectively is proposed.
Japanese Patent Publication No. 7-161185 describes, a proposal is made for realizing high-speed data transmission with low power consumption when the input of the receiver circuit only changes slowly and the operation speed becomes slow when the wiring for data transmission becomes long in a data transmission circuit.
In addition, according to Japanese Patent Publication No. 2004-317910, a signal transmission circuit in a liquid crystal display device which enables high-speed signal transmission without increasing wiring area or power consumption even when the wiring has a high resistance, such as aluminum wiring on a glass substrate, is proposed.
According to Japanese Patent Publication No. 3265181, a clock distribution circuit which reduces clock skew attributed to fluctuations in the transmission delay time of a clock signal due to wiring and reduces internal delay of the clock signal attributed to increase in wiring resistance due to miniaturization of the process, even when the wiring lengths are the same, is proposed.
However, there is a problem in that the number of stages in the clock tree increases and the internal delay of the clock signal within the integrated circuit 76 increases with the increase in the circuit size of the integrated circuit 76 to which the clock signal is input, and the circuit becomes unsuitable for high-speed operations.
In addition, in conventional circuits using multiple-stage inverters, buffers, etc, the signals do not reach full amplitude during transmission due to insufficient bandwidth in the transmission circuit and the like. Therefore, there is a problem in that the common-mode voltage of the clock signal is not stable.
In addition, with regards to voltage and amplitude, it is necessary to consider: 1) the output voltage amplitude and common-mode voltage of the circuit generating the clock signal (in this case, VCO); 2) the voltage amplitude and common-mode voltage facilitating transmission in the circuit transmitting the clock signal; and 3) the voltage amplitude and common-mode voltage desired by the circuit receiving the clock signal.
Thus, because the operating speeds of the clock generating circuit and the circuit receiving the clock signal increase when the frequency of the clock signal increases, the accuracy of the operation timing of the circuit must be increased. Thus, although the importance of fulfilling the three conditions above increases, the distribution of the clock signal becomes more difficult due to insufficient bandwidth in the circuit. In addition, according to Patent References 1 to 3, the foregoing issues are not resolved by configuring the clock distribution circuit with the same transistor (such as MOSFET) configuration (topology).